Turbo encoder and related methods

ABSTRACT

A turbo encoder comprising multiple interleaved parallel concatenated recursive systematic convolutional encoder wherein each recursive systematic convolutional encoder is provided with an LUT that simultaneously provides the output bit pattern as well as the next state value corresponding to a defined set of multiple input bits and present state for operating said recursive systematic convolutional encoder. Thus the approach works with improved LUTs, which do the job of both puncturing and multiplexing for four input bits at a time. Theoretically the proposed approach works almost four times faster than the conventional approach, which can handle only one input bit at a time.

FIELD OF THE INVENTION

The present invention relates to an improved turbo encoder and relatedmethods.

BACKGROUND OF THE INVENTION

Turbo coding is an advanced error correction technique widely used inthe communications industry. Turbo encoders and decoders are keyelements in today's communication systems to achieve the best possibledata reception with least possible errors. The basis of turbo coding isto introduce redundancy in the data to be transmitted through a channelby serial/parallel concatenation of convolutional encoders. Using thisredundant data the component decoders working in iterative passion helpsto recover original data from the received data. This feature makesturbo encoding all the more popular.

FIG. 1 shows a WCDMA turbo encoder specified in 3GPP TS 25.212specifications entitled “Multiplexing and channel coding (FDD)”. WCDMAturbo encoder is parallel-concatenated recursive systematicconvolutional encoder (RSC) with random interleaver in between. Thefirst RSC (3) works on actual input data and the second RSC (4) works oninterleaved data provided by the interleaver (2).

The input to the turbo encoder (1) is a 32-bit packet and the outputfrom the turbo encoder (1) is also a 32-bit packet resulting frommultiplexed output of both RSCs (3 & 4) by puncturing the non-systematicbit of the second RSC (4). As one stream of input bit results in threeoutput bit streams, the rate of this turbo code is 1/3. After finishingencoding of the input bits both the RSCs (3 & 4) are flushed out suchthat the state of both RSCs (3 & 4) becomes zero. While flushing theencoder (1), the output tail bits of the first RSC (3) systematic bitfollowed by parity bit are packed along with the encoded stream.Similarly the output tail bits of second RSC (4) non-systematic bitfollowed by parity bit are packed to the output stream.

In a conventional approach, the parity output of the RSC with respect tostate, follows 1^(st) order Markov chain. The conventional approach usesa LUT which gives next state and the output for the given input andpresent state. The WCDMA turbo encoder table is given in FIG. 2. Theinput to the 1^(st) RSC is given bit by bit from the input data and theinput to the 2^(nd) RSC is given from the input data by using precalculated interleaver table. The input systematic bit is packed withthe output parity bits of both the RSCs in an output register.

As both input and output are 32 bit packed and each encoder parityoutput depends on the present state, the implementation involves manylogical, shift and memory read/write operations. It requires at leastone memory read for encoding single bit to get output or next stateinformation for each RSC and also needs masking of the required bits andshifting to their respective positions and packing with the outputregister. The above steps are repeated 32 times to process each 32 bitpacked input and whenever the output register is full of 32 bits it isstored to the output array.

Further the conventional approach used for implementing turbo codingprocesses one input bit at a time. This is not the best way and consumeslot of operations. A new approach, which works on four input bits at atime, has been proposed.

SUMMARY OF THE INVENTION

To obviate the aforesaid drawbacks, the object of the instant inventionis to provide an improved turbo encoder

Another object of the invention is to provide an encoder that operateson multiple bits simultaneously.

To achieve the aforementioned objects the invention provides An improvedturbo encoder comprising multiple interleaved parallel concatenatedrecursive systematic convolutional encoder wherein each recursivesystematic convolutional encoder is provided with an LUT thatsimultaneously provides the output bit pattern as well as the next statevalue corresponding to a defined set of multiple input bits and presentstate for operating said recursive systematic convolutional encoder.

The said LUT is shared across multiple recursive systematicconvolutional encoder.

An improved method for turbo encoding comprising the steps of:

-   -   determining a first output bit pattern corresponding to received        multiple input bits of input bit stream employing an LUT;    -   interleaving the said input bit stream to provide multiple        interleaved output bit streams;    -   determining a second output bit pattern for multiple bits of        each said multiple interleaved output bit stream employing an        LUT;    -   generating the output bit stream from said primary and secondary        output bit patterns wherein all the output bit patterns are        generated using LUTs operating on a set of multiple bit at a        time.

Each said output bit pattern of said LUT is generated by a state machinefor multiple input bits.

The said LUT provides the next state information generated by said statemachine as per multiple input bits and present state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a WCDMA turbo encoder specified in 3GPP TS 25.212specifications.

FIG. 2 describes a WCDMA turbo encoder table for calculating next stateand parity output.

FIG. shows an output word format after completion of turbo encoding for32 bit input word.

FIG. 4 shows a first RSC's LUT for calculating next state and the outputpattern.

FIG. 5 shows a second RSC's LUT for calculating next state and theoutput pattern.

FIG. 6 shows an output word packing using patterns obtained from bothRSCS.

FIG. 7 shows an output pattern for LUT1 and LUT2.

FIG. 8 shows a CDMA2000 Turbo encoder specified in 3GPP2 C.S0002-D.

FIG. 9 shows an output pattern for LUT1 and LUT2 for rate 1/2 CDMA2000turbo encoder.

FIG. 10 shows an output pattern for LUT1 and LUT2 for rate 1/5 CDMA2000turbo encoder.

FIG. 11 shows an output pattern for LUT1 and LUT2 for rate 1/4 CDMA2000turbo encoder.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The instant invention is explained for encoding four bits simultaneouslyat the rate 1/3 as an example. However it is not limited to said valuesand any person skilled in the art can use it for other rates anddifferent number of bits as well. The proposed approach can be extendedto implement encoding in different applications like CDMA2000 turboencoder.

FIG. 2 shows the input and output words being encoded at the rate of1/3. The encoding of complete 32 bit word, results in three 32 bitoutput words. The S_(j) is the j^(th) systematic bit; P_(j) ¹ is parityoutput of first RSC and P_(j) ² is parity output of second RSC.

The systematic input, parity output of first RSC (3) and the second RSC(4) are distributed amongst the three output words, each separated bytwo bits. Thus four input bits are continuously encoded with each RSC (3or 4) following its own LUT for calculating output pattern of 12 bitseach. The result of both RSCs (3 & 4) is ‘OR’ed to obtain the actualoutput pattern. The abovementioned LUT also provides the next-stateinformation apart from the output pattern.

The LUTs for both RSCs (3 & 4) of turbo encoder shown in FIG. 1 areshown in FIGS. 4 & 5 respectively for only few combinations of the inputand the present-state. The LUT of first RSC (3) contains systematic andparity output bits for the four continuous input bits. The LUT of secondRSC (4) contains only parity output bits for four continuous input bitsas non-systematic bits are punctured. The description of the tableformation is explained in detail in the next section.

The approach works in two parts. Since the input is an array of 32 bits,the input bits, which are complete 32 bit packed are handled in firstpart and the incomplete bits in last word are handled in the secondpart. The proposed new approach is used in the first part and theconventional approach is used for the second part.

Since a nibble of four bits is encoded at a time, the inner loop runseight times to finish the encoding of 32 bits resulting in eight outputpatterns and the outer loop runs the number of times the number of wordsare to be encoded. The non-systematic input bits to the second RSC (4)are packed into 32 bit register using pre-calculated interleaver tablebefore the onset of the encoding of the inner loop. Once encoding of theinner loop is completed, all the eight output patterns are packed intothe three words. The output words are packed from patterns according tothe word boundaries, as shown in FIG. 6. Thus the outer loop includesthe non-systematic bit packing and output packing apart from encodingthe inner loop. The remaining bits in last incomplete word can at mostbe 31 bits, which can be processed one bit at a time with theconventional method.

LUT Generation

As described above, for every four bits, the output pattern results fromboth RSCs (3 & 4) and the parity output positions therein obtained fromboth the RSCs (3 & 4) are different thereby requiring individual LUTsfor each RSC. Each element of the LUT requires 16 bits, upper 4 bitsrepresent the next-state and the lower 12 bits represents the outputpattern of the corresponding RSC. For a given state there are sixteendifferent combinations of inputs (2⁴=16), and eight such possible statesin case of WCDMA turbo encoder, which is containing 3 memory elements(2³=8). Therefore the table size of each LUT is 256 bytes (128 elementsand each of 2 bytes).

LUT1 for First RSC

For all possible states and input bits, the parity output bits afterevery input bit and next state after four continuous input bits arecalculated using FIG. 2. As the output steam contains systematic bits,the input bits and parity bits are placed in respective positions tofollow the output word format described in FIG. 3. The positions wherethe parity output from second RSC is to be placed are filled with zeros.Accordingly the LUT1 pattern (6) for first RSC (3) looks as described inFIG. 7.

LUT2 for Second RSC

The LUT2 pattern (7) for second RSC (4) is shown in FIG. 7. The partyoutput bit after every input bit and the next state after fourcontinuous input bits are calculated using FIG. 2. In the second RSC(4), the output is only the parity output. Hence the parity output bitsof second RSC (4) are placed in respective positions and the positionwhere the systematic and parity output bits from first RSC are to beplaced is filled by zeros.

Complexity Analysis and Comparison

The complexity of this approach is analyzed against the conventionalapproach. As per the proposed approach, it encodes 4 bit input patterninto 12 bit output pattern and requires two memory loads, a single ‘OR’operation and a mask operation for the required pattern. The updatingnext state of each RSC takes one mask and one shift operations for every4 input bits. Also, it consumes few more logical operations for packingof non-systematic bits and packing of output patterns into output words.Using conventional approach, each RSC requires one memory read, one maskoperation for the required bit, and one shift operation for therespective position and ‘OR’ operation for packing to the result. Alsofew more logical operations are required for un-packing of systematicinput word.

The proposed approach explained on WCDMA rate 1/3, however runs fourtimes faster than the conventional approach, as it requires only onefourth of the operations. Further it can be extended to other standardssuch as CDMA2000 turbo encoding which supports various rates bypuncturing.

The CDMA2000 turbo encoder shown in FIG. 8 supports various coding rates1/2, 1/3, 1/4 and 1/5 with two feed forwards polynomials (8 & 9)(1+D+D³, 1+D+D²+D3) and one feed back polynomial (10) (1+D²+D³). Theproposed LUTs are used for encoding. The calculation of contents of bothLUTs is explained further. Care should be taken according to the codingrate and puncturing while calculating output pattern of LUTs.

The output streams for different rates from CDMA2000 turbo encoder lookas follows.

-   For rate 1/2: X₁, Y₁, X₂, Y′₂, X₃, Y₃, X₄, Y′₄-   For rate 1/3: X₁, Y₁, Y′₁, X₂, Y₂, Y′₂, X₃, Y₃, Y′₃, X₄, Y₄, Y′₄-   For rate 1/4: X₁, Y₁, Z₁, Z′₁, X₂, Y₂, Y′₂, Z′₂, X₃, Y₃, Z₃, Z′₃,    X₄, Y₄, Y′₄, Z′₄-   For rate 1/5: X₁, Y₁, Z₁, Y′₁, Z′₁, X₂, Y₂, Z₂, Y′₂, Z′₂, X₃, Y₃,    Z₃, Y′₃, Z′₃, X₄, Y₄, Z₄, Y′₄, Z′₄

For rate 1/3, the LUTs remain the same as that of WCDMA as there is nodifference in encoding. In case of rate 1/2, along with systematic bitX_(i) either the parity of RSC1 Y_(i) or RSC2 Y′_(i) is sentalternatively. Each element of LUT requires 16 bits, upper 4 bitsrepresents the next-state while the lower 8 bits represent outputpattern of the corresponding RSC as shown in FIG. 9 and remaining 4 bitsare unused. Zeros in LUTs fill the unused portion of bits. After packingsuch eight output patterns, the output of complete 32 bit word input isformed into two 32 bit output words (8*8 bits=64 bits). The table sizeof each LUT required is 256 bytes (128 elements and each of 2 bytes).

For the rate 1/5 each element of LUT requires more than 16 bits so theelement size can be 32 bits. The upper 4 bits represents the next-statewhile the lower 20 bits represents output pattern of corresponding RSCas shown in FIG. 10. After packing eight such output patterns the outputof complete 32 bit word input is formed into five 32 bit output words(8*20 bits=160 bits). The table size of each LUT required is 512 bytes(128 elements and each of 4 bytes).

For rate 1/4 also each element of LUT requires more than 16 bits so theelement size can be 32 bits. The upper 4 bits represents the next-statewhile the lower 16 bits represents the output pattern of correspondingRSC as shown in FIG. 11. After packing eight such output patterns theoutput of complete 32 bit word input is formed into four 32 bit outputwords (8*16 bits=128 bits). The table size of each LUT required is 512bytes (128 elements and each of 4 bytes).

In this paper, improved turbo encoding has been proposed and comparedagainst the computations required with conventional method. Thisimproved turbo encoding handles 4 bits at a time, and the same logic canbe extended for 8 input bits at a time, as the cost of 32 times memory,which is not advisable. The proposed approach is described in detail forWCDMA turbo encoder. A brief idea for implementing this in otherstandards such as CDMA2000, which can support other coding rates such as1/2, 1/4 and 1/5 apart from 1/3, is also presented. The approach worksefficiently for all coding rates, as the LUT inherently does the job ofpuncturing and multiplexing according to the coding rate.

1. An improved turbo encoder comprising interleaved parallelconcatenated recursive systematic convolutional encoder wherein eachrecursive systematic convolutional encoder is provided with an LUT thatsimultaneously provides the output bit pattern as well as the next statevalue corresponding to a defined set of multiple input bits and presentstate for operating said recursive systematic convolutional encoder. 2.An improved turbo encoder comprising multiple interleaved parallelconcatenated recursive systematic convolutional encoder as claimed inclaim 1 wherein said LUT is shared across multiple recursive systematicconvolutional encoder.
 3. An improved method for turbo encodingcomprising the steps of: determining a first output bit patterncorresponding to received multiple input bits of input bit streamemploying an LUT; interleaving the said input bit stream to providemultiple interleaved output bit streams; determining a second output bitpattern for multiple bits of each said multiple interleaved output bitstream employing an LUT; generating the output bit stream from saidprimary and secondary output bit patterns wherein all the output bitpatterns are generated using LUTs operating on a set of multiple bit ata time.
 4. An improved method for turbo encoding as claimed in claim 3wherein each said output bit pattern of said LUT is generated by a statemachine for multiple input bits.
 5. An improved method for turboencoding as claimed in claim 3 wherein said LUT provides the next stateinformation generated by said state machine as per multiple input bitsand present state.